Silicon Canvas Introduces Process Test Chip Development Tool Laker T1
Santa Clara, Calif. - December 8, 2003 - Silicon Canvas® Incorporated today announced its Laker® T1 product, a platform for Process Test Chip Development (PTD). Laker T1 is the first commercial product of its kind. It can be used by pure foundries houses and IDM companies to calibrate and qualify IC process technologies. It can be also used by cutting-edge fabless houses which have special devices of their own kind.
Based on its relationships with the world's leading foundries such as TSMC, Silicon Canvas developed Laker T1 to enhance and streamline the conventional PTD flow. With Laker T1, cycles that usually took two years and three to six re-spins in the conventional flow can be shortened to eight months or less and with only zero or one re-spin. Clients using T1 can realize a huge ROI from equipment depreciation alone, let alone other intangible benefits such as better yield, early time-to-market gains, and more flexible business models.
"Laker T1 has made Process Test Chip Development easier to standardize, parameterize and reuse the test structures to accommodate any new process requirements," says Dr. K.L. Young, director of Research & Development at TSMC.
"Through Laker T1, we offer automation and correct-by-construction test chip layout implementation resulting in a standardized Process Test Chip Development platform that can be re-used at any process derivatives and future technology nodes," said Dr. Hau-Yung Chen, President of Silicon Canvas.
Economics of Process Test Chip Development escalating
The PTD cycle is quickly becoming one of the leading barriers to market success for pure foundries houses and IDM companies. Escalating development costs combined with longer development lead times prohibit many fabs from placing complete and thoroughly scrutinized test structures and test lines into the test chips. The problem continues to feed on itself as the lack of critical correlation and test data makes their way though the PTD cycle.
For example, a 300mm (12 in.) wafer fab costs between $2B and $4B to build. Typical mask costs range from $750K for 130nm to $3M for 65nm. The conventional PTD models, most of which are created by trial-and-error, can take as long as 2 years to complete and require 3 to 6 correction spins - a methodology that obviously is no longer cost effective.
Designers who are using the services of a fab require a Process Test Chip Development approach that can reduce the re-spins and shorten the overall PTD cycle, while providing a systematic way to generate sufficient and meaningful data required to qualify a fab.
With Laker T1's systematic reusable and scalable approach, foundries can easily create multitudes of test structures and test lines targeted at providing detailed coverage of the many different aspects of PTD (see "Laker T1 Features and Benefits" section below). This will aid in obtaining faster convergence between the process' electrical performance and equipment resolution. In turn, the foundry can deliver a more comprehensive specification to the customer with overall increased confidence in design for manufacturability. The bottom line is a faster ramp-up time.
Need for streamlined Process Test Chip Development platform
Test chips play a pivotal role in Process Test Chip Development. They are used to find the "manufacturing" resolution minimums posed by equipment and materials. They are also used to generate real electrical data to be correlated with simulation data. The conventional approach for PTD falls into two models: in-house development and out-sourcing service.
The out-sourcing approach is not an appealing option for top-tier foundries or semiconductor houses. The knowledge base is rarely transferred - from outside vendor back to the foundry or semiconductor house -- in its complete form and the expense does not contribute to a reduction in costs for future PTD efforts. Perhaps the most compromising aspect of the outsourcing model is the fact that the company may have to reveal some of its most prized intellectual property - test structures for cutting-edge processes. Therefore, most top-tier companies use an in-house approach.
Because current software tools are not designed for Process Test Chip Development, these top-tier companies are generally forced to use a combination of in-house developed software, general-purpose design tools, and much manual work. Such a process results in a grave level of inefficiency and inaccuracy. Moreover, the typical internal-development approach usually involves people with different backgrounds from a variety of engineering groups. This can become a nightmare for consistency in communication. Documentation begins to lag behind the progress of the Process Test Chip Development, and, quite often, the final result is an incomplete spec., incomplete documentation, and little reuse of information for subsequent process migration.
Whether in-house or out-sourcing models are employed, the conventional Process Test Chip Development approach also makes the technology transfer extremely difficult and therefore limits the scope of business the foundry can conduct.
Laker T1 features and benefits
Laker T1 provides a complete, integrated solution for Process Test Chip Development because it can do test structures, test lines, document all in one tool. Using its patent-pending parameterized test structure technique, the user can visually build parameterized test structures and test lines rapidly. Once created, these test structures and test lines can be scaled across different process geometries. As examples, one can scale from 90nm standard logic down to 65nm, or scale up to 0.13um mixed-signals by simply changing a few parameters and/or variable settings.
Once test structures are parameterized and stored in the central controlled database, Laker T1 provides an easy-to-use WYSWYG environment that allows users to specify any configuration of the probe card, the connectivity, and locations of the master test structures. These parameterized test line configurations can be previewed or modified easily before being realized into the physical structures with Laker T1's built-in patented tapering router. This correct-by-construction approach ensures no open/short errors on test lines.
The often-neglected portion in any project is documentation. Laker T1 automatically generates documentation in HTML and Microsoft word formats, which will always sync up with test structures and test lines.
Laker T1 is designed for ease-of-use and can be adopted immediately into a user's existing Process Test Chip Development flow. The tool comes with a complete set of generic public domain test structures. Laker T1's unique architecture and data scheme provide a central reservoir for all test chip information while preserving access privilege of sensitive process information to authorized parties. This methodology enables corporation-wide technology knowledge management as well as intellectual property control.
Pricing and Availability
Laker T1 is available now. Pricing starts at $1,000,000 for a three-year license. Service is also available at an additional fee. Laker T1 is supported on the Sun Solaris, HP-UX, and Linux platforms.
About Laker T1
Laker T1 delivers at least a ten-fold productivity gain (over current manual methods) in test chip implementation through reusable, transferable and manageable architecture with centralized access control. Laker T1 provides an intuitive user interface to define parameterized test structures and test lines, which speed up technology time to market while allowing last-minute test chip specification change.
About Silicon Canvas
Silicon Canvas is the technology leader in providing Process Test Chip Development platforms and full-custom layout solutions for products and services. It is a California corporation founded in 2000 by Dr. Hau-Yung Chen and other EDA veterans with combined 50+ years of custom design and EDA experiences.
The Company's custom layout solution, Laker T1, addresses the needs of today's analog, mixed signals and large, complex IC, ASIC, and SoC designs. Laker T1 provides more automation and high performance, high capabilities to any design projects, which requires the use of full custom layout editors, including but not limited to the layout creation for analog, mixed signal, and test key designs. Customers' applications include processors, computing systems, networking, telecommunications and graphics. Silicon Canvas is headquartered in San Jose, Calif. For more information please visit Silicon Canvas' web site at www.sicanvas.com or send email to info@sicanvas.com.
For more information, contact
Hau Yung Chen
Silicon Canvas
408-321-0888
Hchen@sicanvas.com
Ed Lee (ed@leepr.com)
Holly Goodliffe (holly@leepr.com)
Lee Public Relations
650-363-0142
